The present invention relates generally to methods of analyzing selected regions of conductor-insulator-semiconductor systems or other semiconductor systems.
Many semiconductor devices require a high quality, well-characterized interface between a conductor and a semiconductor. Examples of such devices are field-effect transistors, computer memory devices, charge-coupled devices, Schottky diodes, and most integrated circuits. Most of these devices are conductor-insulator-semiconductor (CIS) devices. In most CIS devices the conductor is a metal, and thus such devices are commonly referred to as MIS, (metal-insulator-semiconductor) devices. When the semiconductor is silicon and the insulator is silicon oxide, these devices are referred to by the acronym MOS.
In most of these semiconductor devices it is desirable to have no trapped charges in the region between the metal conductor and the semiconductor. Also, it is usually desirable to minimize structural defects, which are often manifest as electric dipoles or trapped charges within the semiconductor or near the interface with either the insulator or the conductor. If trapped charges or defects are present, in most semiconductor devices they should be uniformly distributed so as to produce a uniform electric field or electronic band bending within the semiconductor.